1. Field of the Invention
The present invention relates to the field of manufacturing semiconductor device, and particularly, to an alignment mark employed in a photolithography process and methods of positioning the alignment mark on a mask and a semiconductor wafer.
2. Description of the Related Art
Photolithography, a key technique of large-scaled integrated circuit manufacturing, determines largely how integrated an integrated circuit can be. Photolithography refers to transferring through exposure a mask pattern to a wafer coated with a photoresist, such that the mask pattern will appear on the wafer after development.
A key step in photolithography is alignment of the mask and the wafer. In the manufacture of integrated circuits, it is commonly required to expose multiple layers of mask patterns on a wafer to form a complete circuit structure. In such a multi-photolithography process, with respect to each of the photolithography processes subsequent to the first one, it is necessary to accurately align the mask to be employed in a respective photolithography process with a first layer of a pattern or one of the several previous layers of the pattern exposed on the wafer before proceeding with the respective subsequent photolithography process. The complexity and functional density of the resulting integrated circuits are determined by the accurate registration of various photolithography masks.
At present, two kinds of alignment modes are mainly being used in a photolithography process, namely, zero mark alignment and scribe lane mark alignment. In zero mark alignment, generally only a first layer of pattern has an alignment mark such as XPA (extended primary mark) disposed therein all other subsequent layers are aligned with the first layer. The zero mark is commonly formed on a margin region of the pattern.
However, in devices with a multilayer circuit structure, the signal intensity of a zero mark is usually deteriorated significantly by subsequent metal or passivation layers, leading to difficulty in accurate alignment. In order to overcome such a problem in the prior art, extra photolithography or etching processes need to be applied to reveal the alignment mark regions. However, these extra processes can increase cost and processing time, as a result reducing productivity.
In scribe lane mark alignment, an alignment mark, such as bar type SPM (scribe lane primary mask), is formed in the scribe lanes of each layer or several layers. A pattern layer can be aligned with the alignment mark from one of previous layers.
Nevertheless, with the limitations of photolithography equipment and processes per se, a scribe lane alignment mark such as SPM generally has a constant dimension, such as 80 μm. In order to improve gross dies on a wafer, it is desirable to have the size of scribe lanes less than 80 μm, such as 72 μm, or even 60 μm. In this situation, common SPM alignment marks cannot be accommodated in such small scribe lanes.
Therefore, it is desired to provide a photolithography alignment approach which is applicable to wafers with small sized scribe lanes with high registration accuracy.